1. Field of the Invention
The invention relates to a digital phase locked loop for generating an output frequency using a digitally controlled oscillator.
2. Description of the Known Technology
Digital phase locked loops, known as PLLs, are used in a large number of integrated circuits. PLLs are used as clock and frequency synthesizers, clock generators and clock multipliers. PLLs are employed in time, data and clock recovery circuits and are also used in reception and transmission circuits in phase modulated or frequency modulated systems.
Current applications use analog PLLs, which comprise a phase/frequency detector (PFD) which compares the output frequency of a voltage controlled oscillator (VCO) to a reference frequency and, as output signal, generates a voltage which contains the information for the phase and frequency difference between the output frequency of the voltage controlled oscillator and the reference frequency. The voltage signal is supplied to a charge pump (CP) which converts the voltage signal into a corresponding current signal. This current signal is supplied to a loop filter (LF) whose output signal actuates the voltage controlled oscillator. The feedback path between the voltage controlled oscillator and the phase/frequency detector may contain a frequency divider with a division factor N. In the locked state of the PLL, the output frequency of the voltage controlled oscillator corresponds to N times the reference frequency.
Attempts have been made to design and implement fully integrated PLLs. In this context, the use of modern CMOS technologies is subject to conditions (for example reduced voltage and power supply, gate leakage currents, reduced gm*r product (gain)) which are less favorable for analog circuits than for digital circuits. Future CMOS technologies will provide faster nMOS and pMOS transistors, which are excellently suited to digital circuits. In addition, more than eight metal layers will be implementable, which allow spiral shaped inductor structures, and there is the option of implementing MOS varactor fields. This favors the implementation of digitally controlled VCOs, known as DCOs (Digital Controlled Oscillator), in comparison with analog oscillators.
Patent specification DE 100 22 486 C1 discloses a digital phase locked loop which can be implemented in integrated form. The phase detector device in this circuit comprises an essentially analog phase/frequency detector.
U.S. Pat. No. 6,429,693 discloses a further digital PLL which is compatible with modern sub μ CMOS technologies. The digital phase/frequency detector comprises a time to digital converter whose resolution is given by the switching delay of an inverter implemented in the CMOS process.
In such digital phase/frequency detectors, a digital word representing the reference frequency is subtracted from a digital word which relates to the (possibly divided) output frequency of the digitally controlled oscillator in order to generate the phase/frequency error value which corresponds to the output signal from an analog phase/frequency detector. The primary drawback of this practice is the occurrence of uncontrollable spurious frequencies which arise on account of the finite word length of the digital words which are to be subtracted from one another.
The publication “Delta Sigma Modulation in Fractional N Frequency Synthesis”, T. A. Riley, M. A. Copeland and T. A. Kwasniewski, Journal of Solid State Circuits (JSSC), volume 28, No. 5, pages 553 to 559, May 1993, describes the use of a delta sigma modulator for the signal actuating a frequency divider. The frequency divider is in the form of a dual modulus divider. The delta sigma modulation reduces the influence of spurious frequencies in comparison with known fractional N dividers in phase locked loops.
The publication “An Oversampling Delta Sigma Frequency Discriminator”, R. D. Beards, M. A. Copeland, IEEE Transactions on Circuits and Systems II.: Analog and Digital Signal Processing, volume 41, No. 1, pages 26 to 32, January 1994, specifies a frequency divider circuit which comprises a dual modulus frequency divider and a phase comparator which is connected downstream of the frequency divider. The implementation advantage of this circuit is that dual modulus frequency dividers are relatively simple digital circuits which can be operated at high frequency (several gigahertz) with low power consumption. The frequency decision maker is used in the front end of an intermediate frequency heterodyne receiver.